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. 2020 Mar 2;15(3):e0229645.
doi: 10.1371/journal.pone.0229645. eCollection 2020.

HMB in DRAM-less NVMe SSDs: Their usage and effects on performance

Affiliations

HMB in DRAM-less NVMe SSDs: Their usage and effects on performance

Kyusik Kim et al. PLoS One. .

Abstract

Solid-state drives (SSDs) that do not have internal dynamic random-access memory (DRAM) are being widely spread for client SSD and embedded SSD markets in recent years because they are cheap and consume less power. Obviously, their performance is lower than conventional SSDs because they cannot exploit advantages of DRAM in the controller. However, this problem can be alleviated by using host memory buffer (HMB) feature of Non-Volatile Memory Express (NVMe), which allows SSDs to utilize the DRAM of host. In this paper, we show that commercial DRAM-less SSDs clearly exhibit worse I/O performance than SSDs with internal DRAM, but this can be improved by using the HMB feature. We also present methods that reveal how the host memory buffer is used in commercial DRAM-less SSDs to improve I/O performance. Through extensive experiments, we conclude that DRAM-less SSDs evaluated in this study mainly exploit the host memory buffer as an address mapping table cache rather than a read cache or write buffer to improve I/O performance.

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Conflict of interest statement

The authors have declared that no competing interests exist.

Figures

Fig 1
Fig 1. Architecture of DRAM-less SSD supporting HMB.
Fig 2
Fig 2. I/O performance comparison of DRAM-less SSDs (SSD-A, SSD-B, SSD-C) and SSDs with internal DRAM (SSD-D, SSD-E, SSD-F).
(a) LIGHT, sequential read, (b) LIGHT, sequential write, (c) LIGHT, random read, (d) LIGHT, random write, (e) HEAVY, sequential read, (f) HEAVY, sequential write, (g) HEAVY, random read, and (h) HEAVY, random write.
Fig 3
Fig 3. Some scenarios by read requests.
Fig 4
Fig 4. An algorithm for testing the existence of a read cache.
Fig 5
Fig 5. Test results for the existence of a read cache in the HMB of various SSDs.
(a) SSD-A, with HMB, (b) SSD-B, with HMB, (c) SSD-C, with HMB, (d) SSD-A, without HMB, (e) SSD-B, without HMB, and (f) SSD-C, without HMB.
Fig 6
Fig 6. Some scenarios by write requests.
Fig 7
Fig 7. An algorithm for testing the existence of a write buffer.
Fig 8
Fig 8. Test for existence of write buffer in the host memory buffer.
(a) SSD-A, with HMB, (b) SSD-B, with HMB, (c) SSD-C, with HMB, (d) SSD-A, without HMB, (e) SSD-B, without HMB, and (f) SSD-C, without HMB.
Fig 9
Fig 9. An algorithm for testing the existence of a mapping table cache.
Fig 10
Fig 10. Test for existence of mapping table cache in HMB.
(a) SSD-A, (b) SSD-B, and (c) SSD-C.

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